104 research outputs found
Network Time Synchronization: A Full Hardware Approach
Complex digital systems are typically built on top of several
abstraction levels: digital, RTL, computer, operating system and
software application. Each abstraction level greatly facilitates the design
task at the cost of paying in performance and hardware resources usage.
Network time synchronization is a good example of a complex system
using several abstraction levels since the traditional solutions are a software
application running on top of several software and hardware layers.
In this contribution we study the case where a standards-compliant network
time synchronization solution is fully implemented in hardware on
a FPGA chip doing without any software layer. This solution makes it
possible to implement very compact, inexpensive and accurate synchronization
systems to be used either stand-alone or as embedded cores.
Some general aspects of the design experience are commented together
with some figures of merit. As a conclusion, full hardware implementations
of complex digital systems should be seen as a feasible design
option, from which great performance advantages can be expected, provided
that we can find a suitable set of tools and control the design
development costs
Fast Hardware Implementations of Static P Systems
In this article we present a simulator of non-deterministic static P systems
using Field Programmable Gate Array (FPGA) technology. Its major feature
is a high performance, achieving a constant processing time for each transition. Our
approach is based on representing all possible applications as words of some regular
context-free language. Then, using formal power series it is possible to obtain the
number of possibilities and select one of them following a uniform distribution, in
a fair and non-deterministic way. According to these ideas, we yield an implementation
whose results show an important speed-up, with a strong independence from
the size of the P system.Ministry of Science and Innovation of the Spanish Government under the project TEC2011-27936 (HIPERSYS)European Regional Development Fund (ERDF)Ministry of Education of Spain (FPU grant AP2009-3625)ANR project SynBioTI
Inertial and Degradation Delay Model for CMOS Logic Gates
The authors present the Inertial and Degradation
Delay Model (IDDM) for CMOS digital simulation. The
model combines the Degradation Delay Model presented in
previous papers with a new algorithm to handle the inertial effect,
and is able to take account of the propagation and filtering
of arbitrarily narrow pulses (glitches, etc.). The model clearly
overcomes the limitations of conventional approaches
Modeling of Real Bistables in VHDL
A complete VHDL model of bistables including their
metastable operation is presented. An RS-NAND latch
has been modelled as a basic structure, orienting its
implementation towards its inclusion in a cell library.
Two applications are included: description of a more
complex latch (D-type) and description of a circuit containing
three latches where metastable signals are propagated.
Simulation results show that the presented niodel
provides very realistic information about the device
behavior, which until now had to be obtained through
electric simulation
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
This communication shows the influence of clocking schemes on the
digital switching noise generation. It will be shown how the choice of a suited
clocking scheme for the digital part reduces the switching noise, thus alleviating
the problematic associated to limitations of performances in mixed-signal
Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain
using both a single-phase and a two-phase clocking schemes, as well as of two nbit
counters with different clocking styles lead, as conclusions, to recommend
multiple clock-phase and asynchronous styles for reducing switching noise
New CMOS VLSI Linear Self-Timed Architectures
The implementation of digital signal processor circuits
via self-timed techniques is currently a valid altemative
to solve some problems encountered in synchronous
VLSI circuits. However; a main difference between synchronous
and asynchronous circuits is the hardware resources
needed to implement asynchronous circuits. This
communication presents four less-costly alternatives to a
previously reported linear selftimed architecture, and
their application in the design of FIFO memories. Furthermore,
the integration and characterization in the laboratory
of prototypes of these FIFOs are presented
NanoFS: a hardware-oriented file system
NanoFS is a novel file system for embedded systems and storage-class memories
(like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve an optimal
hardware implementation of the file system’s file lookup and data fetch operations. File system spe-cification on a sample reader module completely implemented in a pro-grammable device is introduced
Delay degradation effect in submicronic CMOS inverters
This communication presents the evidence of a degradation effect causing important
reductions in the delay of a CMOS inverter when consecutive input transition are close
in time. Complete understanding of the effect is demonstrated, providing a quantifying
model. Fully characterization as a function of design variables and external conditions
is carried out, making the model suitable for using in library characterization as well as
simulation at a transistor level. Comparison with HSPICE level 6 simulations shows
satisfactory accuracy for timing evaluation.Comisión Interministerial de Ciencia y Tecnología TIC 95-009
Minimalistic SDHC-SPI hardware reader module for boot loader applications
This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable
Systems on Chip. The proposed module allows loading the system code and data from a standard SD card
without having to re-program the whole embedded system. The hardware boot loader is processor independent
and removes the need of a software boot loader and the related memory resources. The hardware overhead
introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The
implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is
offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller
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